Time-to-digital converters are designed to generate a digital representation of a time interval elapsing between two events. TDC's discretize time intervals, just as analog-to-digital converters (ADC's) discretize analog signal amplitudes. The difference between an actual time interval and the discretized version of that time interval is known as the quantization error, and is determined by the TDC resolution.
Recently, TDC's have found application in the design of all-digital phase-locked loops (ADPLL's), wherein a TDC is used to measure the time difference between an event in a digitally generated output signal and a corresponding event in a reference signal. In an ADPLL, TDC quantization error may accumulate over time, leading to spurs and other undesirable phenomena in the ADPLL output. It would be desirable to reduce the occurrence of such phenomena arising from TDC quantization error.